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3.1: Resistors and Capacitors

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    Introduction

    One important application of electromagnetic field analysis is to simple electronic components such as resistors, capacitors, and inductors, all of which exhibit at higher frequencies characteristics of the others. Such structures can be analyzed in terms of their: 1) static behavior, for which we can set ∂/∂t = 0 in Maxwell’s equations, 2) quasistatic behavior, for which ∂/∂t is non-negligible, but we neglect terms of the order ∂2 /∂t2 , and 3) dynamic behavior, for which terms on the order of ∂2 /∂t2 are not negligible either; in the dynamic case the wavelengths of interest are no longer large compared to the device dimensions. Because most such devices have either cylindrical or planar geometries, as discussed in Sections 1.3 and 1.4, their fields and behavior are generally easily understood. This understanding can be extrapolated to more complex structures.

    One approach to analyzing simple structures is to review the basic constraints imposed by symmetry, Maxwell’s equations, and boundary conditions, and then to hypothesize the electric and magnetic fields that would result. These hypotheses can then be tested for consistency with any remaining constraints not already invoked. To illustrate this approach resistors, capacitors, and inductors with simple shapes are analyzed in Sections 3.1–2 below.

    All physical elements exhibit varying degrees of resistance, inductance, and capacitance, depending on frequency. This is because: 1) essentially all conducting materials exhibit some resistance, 2) all currents generate magnetic fields and therefore contribute inductance, and 3) all voltage differences generate electric fields and therefore contribute capacitance. R’s, L’s, and C’s are designed to exhibit only one dominant property at low frequencies. Section 3.3 discusses simple examples of ambivalent device behavior as frequency changes.

    Most passive electronic components have two or more terminals where voltages can be measured. The voltage difference between any two terminals of a passive device generally depends on the histories of the currents through all the terminals. Common passive linear twoterminal devices include resistors, inductors, and capacitors (R’s, L’s. and C’s, respectively), while transformers are commonly three- or four-terminal devices. Devices with even more terminals are often simply characterized as N-port networks. Connected sets of such passive linear devices form passive linear circuits which can be analyzed using the methods discussed in Section 3.4. RLC resonators and RL and RC relaxation circuits are most relevant here because their physics and behavior resemble those of common electromagnetic systems. RLC resonators are treated in Section 3.5, and RL, RC, and LC circuits are limiting cases when one of the three elements becomes negligible.

    Resistors

    Resistors are two-terminal passive linear devices characterized by their resistance R [ohms]:

    \[ \mathrm{v}=\mathrm{iR}\]

    where v(t) and i(t) are the associated voltage and current. That is, one volt across a one-ohm resistor induces a one-ampere current through it; this defines the ohm.

    The resistor illustrated in Figure 3.1.1 is comprised of two parallel perfectly conducting endplates between which is placed a medium of conductivity σ, permittivity ε, permeability μ, and thickness d; the two end plates and the medium all have a constant cross-sectional area A [m2 ] in the x-y plane. Let’s assume a static voltage v exists across the resistor R, and that a current i flows through it.

    Figure 3.1.1.PNG
    Figure \(\PageIndex{1}\): Simple resistor.

    Boundary conditions require the electric field\(\overline E\)at any perfectly conducting plate to be perpendicular to it [see (2.6.16); \(\overline{\mathrm{E}} \times \hat{n}=0\)] , and Faraday’s law requires that any line integral of\(\overline E\)from one iso-potential end plate to the other must equal the voltage v regardless of the path of integration (1.3.13). Because the conductivity σ [Siemens/m] is uniform within walls parallel to \(\hat{z}\), these constraints are satisfied by a static uniform electric field \(\overline{\mathrm{E}}=\hat{z} \mathrm{E}_{\mathrm{o}}\) everywhere within the conducting medium, which would be charge-free since our assumed\(\overline E\)is non-divergent. Thus:

    \[ \int_{0}^{\mathrm{d}} \overline{\mathrm{E}} \bullet \hat{z} \mathrm{d} z=\mathrm{E}_{0} \mathrm{d}=\mathrm{v}\]

    where \( \mathrm{E}_{\mathrm{o}}=\mathrm{v} / \mathrm{d}\left[\mathrm{Vm}^{-1}\right]\).

    Such an electric field within the conducting medium induces a current density \(\overline J\), where:

    \[ \overline{\mathrm{J}}=\sigma \overline{\mathrm{E}}\left[\mathrm{Am}^{-2}\right]\]

    The total current i flowing is the integral of \(\overline{\mathrm{J}} \bullet \hat{z} \) over the device cross-section A, so that:

    \[\mathrm{i}=\int \int_{\mathrm{A}} \overline{\mathrm{J}} \bullet \hat{z} \mathrm{d} \mathrm{x} \mathrm{d} \mathrm{y}=\int \int_{\mathrm{A}} \sigma \overline{\mathrm{E}} \bullet \hat{z} \mathrm{d} \mathrm{x} \mathrm{d} \mathrm{y}=\int \int_{\mathrm{A}} \sigma \mathrm{E}_{\mathrm{o}} \mathrm{d} \mathrm{x} \mathrm{d} \mathrm{y}=\sigma \mathrm{E}_{\mathrm{o}} \mathrm{A}=\mathrm{v} \sigma \mathrm{A} / \mathrm{d} \]

    But i = v/R from (3.1.1), and therefore the static resistance of a simple planar resistor is:

    \[\mathrm{R}=\mathrm{v} / \mathrm{i}=\mathrm{d} / \sigma \mathrm{A}\ [\mathrm{ohms}]\]

    The instantaneous power p [W] dissipated in a resistor is i2R = v2/R, and the time-average power dissipated in the sinusoidal steady state is \(|\mathrm{\underline{I}}|^{2} \mathrm{R} / 2=|\mathrm{\underline{V}}|^{2} / 2 \mathrm{R} \) watts. Alternatively the local instantaneous power density \( \) can be integrated over the volume of the resistor to yield the total instantaneous power dissipated:

    \[ \]

    which is the expected answer, and where we used (2.1.17): \( \).

    Surface charges reside on the end plates where the electric field is perpendicular to the perfect conductor. The boundary condition \( \) suggests that the surface charge density ρs on the positive end-plate face adjacent to the conducting medium is:

    \[ \]

    The total static charge Q on the positive resistor end plate is therefore ρsA coulombs. By convention, the subscript s distinguishes surface charge density ρs [C m-2] from volume charge density ρ [C m-3]. An equal negative surface charge resides on the other end-plate. The total stored charged Q = ρsA = CV, where C is the device capacitance, as discussed further in Section 3.1.3.

    The static currents and voltages in this resistor will produce fields outside the resistor, but these produce no additional current or voltage at the device terminals and are not of immediate concern here. Similarly, μ and ε do not affect the static value of R. At higher frequencies, however, this resistance R varies and both inductance and capacitance appear, as shown in the following three sections. Although this static solution for charge, current, and electric field within the conducting portion of the resistor satisfies Maxwell’s equations, a complete solution would also prove uniqueness and consistency with \(\overline H\) and Maxwell’s equations outside the device. Uniqueness is addressed by the uniqueness theorem in Section 2.8, and approaches to finding fields for arbitrary device geometries are discussed briefly in Sections 4.4–6.

    Example \(\PageIndex{A}\)

    Design a practical 100-ohm resistor. If thermal dissipation were a problem, how might that change the design?

    Solution

    Resistance R = d/σA (3.1.5), and if we arbitrarily choose a classic cylindrical shape with resistor length d = 4r, where r is the radius, then A = \(\pi\)r2 = \(\pi\)d2 /16 and R = 16/\(\pi\)dσ = 100. Discrete resistors are smaller for modern low power compact circuits, so we might set d = 1 mm, yielding σ = 16/\(\pi\)dR = 16/(\(\pi\)10-3×100) ≅ 51 S m-1. Such conductivities roughly correspond, for example, to very salty water or carbon powder. The surface area of the resistor must be sufficient to dissipate the maximum power expected, however. Flat resistors thermally bonded to a heat sink can be smaller than air-cooled devices, and these are often made of thin metallic film. Some resistors are long wires wound in coils. Resistor failure often occurs where the local resistance is slightly higher, and the resulting heat typically increases the local resistance further, causing even more local heating.

    Capacitors

    Capacitors are two-terminal passive linear devices storing charge Q and characterized by their capacitance C [Farads], defined by:

    \[\mathrm{Q}=\mathrm{Cv} \ [\text { Coulombs }]\]

    where v(t) is the voltage across the capacitor. That is, one static volt across a one-Farad capacitor stores one Coulomb on each terminal, as discussed further below; this defines the Farad [Coulombs per volt].

    The resistive structure illustrated in Figure 3.1.1 becomes a pure capacitor at low frequencies if the media conductivity σ → 0. Although some capacitors are air-filled with ε ≅ εo, usually dielectric filler with permittivity ε > εo is used. Typical values for the dielectric constant ε/εo used in capacitors are ~1-100. In all cases boundary conditions again require that the electric field E be perpendicular to the perfectly conducting end plates, i.e., to be in the ±z direction, and Faraday’s law requires that any line integral of E from one iso-potential end plate to the other must equal the voltage v across the capacitor. These constraints are again satisfied by a static uniform electric field \(\overline{\mathrm{E}}=\hat{z} \mathrm{E}_{\mathrm{o}}\) within the medium separating the plates, which is uniform and charge-free.

    We shall neglect temporarily the effects of all fields produced outside the capacitor if its plate separation d is small compared to its diameter, a common configuration. Thus Eo = v/d [V m-1] (3.1.2). The surface charge density on the positive end-plate face adjacent to the conducting medium is σs = εEo [C m-2], and the total static charge Q on the positive end plate of area A is therefore:

    \[\mathrm{Q}=\mathrm{A} \sigma_{\mathrm{s}}=\mathrm{A} \varepsilon \mathrm{E}_{\mathrm{o}}=\mathrm{A} \varepsilon \mathrm{v} / \mathrm{d}=\mathrm{Cv}\ [\mathrm{C}] \]

    Therefore, for a parallel-plate capacitor:

    \[ \mathrm{C}=\varepsilon \mathrm{A} / \mathrm{d} \ [\text { Farads }] \qquad \qquad\quad \text{(parallel-plate capacitor) }\]

    Using (3.1.2) and the fact that the charge Q(t) on the positive plate is the time integral of the current i(t) into it, we obtain the relation between voltage and current for a capacitor:

    \[\mathrm{v}(\mathrm{t})=\mathrm{Q}(\mathrm{t}) / \mathrm{C}=(1 / \mathrm{C}) \int_{-\infty}^{\mathrm{t}} \mathrm{i}(\mathrm{t}) \mathrm{d} \mathrm{t} \]

    \[ \mathrm{i}(\mathrm{t})=\mathrm{C} \mathrm{dv}(\mathrm{t}) / \mathrm{d} \mathrm{t}\]

    When two capacitors are connected in parallel as shown in Figure 3.1.2, they are equivalent to a single capacitor of value Ceq storing charge Qeq, where these values are easily found in terms of the charges (Q1, Q2) and capacitances (C1, C2) associated with the two separate devices.

    Figure 3.1.2.PNG
    Figure \(\PageIndex{2}\): Capacitors in parallel.

    Because the total charge Qeq is the sum of the charges on the two separate capacitors, and capacitors in parallel have the same voltage v, it follows that:

    \[\mathrm{Q}_{\mathrm{eq}}=\mathrm{Q}_{1}+\mathrm{Q}_{2}=\left(\mathrm{C}_{1}+\mathrm{C}_{2}\right) \mathrm{v}=\mathrm{C}_{\mathrm{eq}} \mathrm{v} \]

    \[\mathrm{C}_{\mathrm{eq}}=\mathrm{C}_{1}+\mathrm{C}_{2} \qquad\qquad\quad \text { (capacitors in parallel) } \]

    Figure 3.1.3.PNG
    Figure \(\PageIndex{3}\): Capacitors in series.

    When two capacitors are connected in series, as illustrated in Figure 3.1.3, then their two charges Q1 and Q2 remain equal if they were equal before current i(t) began to flow, and the total voltage is the sum of the voltages across each capacitor:

    \[\mathrm{C}_{\mathrm{eq}}^{-1}=\mathrm{v} / \mathrm{Q}=\left(\mathrm{v}_{1}+\mathrm{v}_{2}\right) / \mathrm{Q}=\mathrm{C}_{1}^{-1}+\mathrm{C}_{2}^{-1} \qquad\qquad\quad \text { (capacitors in series) } \]

    The instantaneous electric energy density We [J m-3] between the capacitor plates is given by Poynting’s theorem: \(\mathrm{W}_{\mathrm{e}}=\varepsilon|\overline{\mathrm{E}}|^{2} / 2 \) (2.7.7). The total electric energy we stored in the capacitor is the integral of We over the volume Ad of the dielectric:

    \[ \mathrm{w}_{\mathrm{e}}=\int \int \int_{\mathrm{V}}\left(\varepsilon|\overline{\mathrm{E}}|^{2} / 2\right) \mathrm{d} \mathrm{v}=\varepsilon \mathrm{Ad}|\overline{\mathrm{E}}|^{2} / 2=\varepsilon \mathrm{Av}^{2} / 2 \mathrm{d}=\mathrm{Cv}^{2} / 2 \ [J]\]

    The corresponding expression for the time-average energy stored in a capacitor in the sinusoidal steady state is:

    \[\mathrm{w}_{\mathrm{e}}=\mathrm{C}|\underline{\mathrm{J}}|^{2} / 4 \ [V] \]

    The extra factor of two relative to (3.1.9) enters because the time average of a sinsuoid squared is half its peak value.

    To prove (3.1.16) for any capacitor C, not just parallel-plate devices, we can compute \( \mathrm{w}_{\mathrm{e}}=\int_{0}^{\mathrm{t}} \mathrm{iv} \mathrm{dt}\) where i = dq/dt and q = Cv Therefore \(\mathrm{w}_{\mathrm{e}}=\int_{0}^{\mathrm{t}} \mathrm{C}(\mathrm{dv} / \mathrm{dt}) \mathrm{v} \mathrm{dt}=\int_{0}^{\mathrm{v}} \mathrm{Cv} \mathrm{d} \mathrm{v}=\mathrm{Cv}^{2} / 2 \) in general.

    We can also analyze other capacitor geometries, such as the cylindrical capacitor illustrated in Figure 3.1.4. The inner radius is “a”, the outer radius is “b”, and the length is D; its interior has permittivity ε.

    Figure 3.1.4.PNG
    Figure \(\PageIndex{4}\): Cylindrical capacitor.

    The electric field again must be divergence- and curl-free in the charge-free regions between the two cylinders, and must be perpendicular to the inner and outer cylinders at their perfectly conducting walls. The solution can be cylindrically symmetric and independent of \(\phi\). A purely radial electric field has these properties:

    \[ \overline{\mathrm{E}}(\mathrm{r})=\hat{r} \mathrm{E}_{\mathrm{o}} / \mathrm{r}\]

    The electric potential \(\Phi\)(r) is the integral of the electric field, so the potential difference v between the inner and outer conductors is:

    \[\mathrm{v}=\Phi_{\mathrm{a}}-\Phi_{\mathrm{b}}=\int_{\mathrm{a}}^{\mathrm{b}} \frac{\mathrm{E}_{\mathrm{o}}}{\mathrm{r}} \mathrm{dr}=\left.\mathrm{E}_{\mathrm{o}} \ln \mathrm{r}\right|_{\mathrm{a}} ^{\mathrm{b}}=\mathrm{E}_{\mathrm{o}} \ln \left(\frac{\mathrm{b}}{\mathrm{a}}\right) \ [\mathrm{V}] \]

    This capacitor voltage produces a surface charge density ρs on the inner and outer conductors, where \(\rho_{\mathrm{s}}=\varepsilon \mathrm{E}=\varepsilon \mathrm{E}_{\mathrm{o}} / \mathrm{r}\). If \(\Phi_{\mathrm{a}}>\Phi_{\mathrm{b}}\), then the inner cylinder is positively charged, the outer cylinder is negatively charged, and Eo is positive. The total charge Q on the inner cylinder is then:

    \[\mathrm{Q}=\rho_{\mathrm{s}} 2 \pi \mathrm{aD}=\varepsilon \mathrm{E}_{\mathrm{o}} 2 \pi \mathrm{D}=\varepsilon \mathrm{v} 2 \pi \mathrm{D} /[\ln (\mathrm{b} / \mathrm{a})]=\mathrm{CC} \ [v] \]

    Therefore this cylindrical capacitor has capacitance C:

    \[\mathrm{C}=\varepsilon 2 \pi \mathrm{D} /[\ln (\mathrm{b} / \mathrm{a})][F] \qquad \qquad \quad \text { (cylindrical capacitor) } \]

    In the limit where b/a → 1 and b - a = d, then we have approximately a parallel-plate capacitor with C → εA/d where the plate area A = 2\(\pi\)aD; see (3.1.10).

    Example \(\PageIndex{B}\)

    Design a practical 100-volt 10-8 farad (0.01 mfd) capacitor using dielectric having ε = 20εo and a breakdown field strength EB of 107 [V m-1].

    Solution

    For parallel-plate capacitors C = εA/d (3.1.10), and the device breakdown voltage is EBd = 100 [V]. Therefore the plate separation d = 100/EB = 10-5 [m]. With a safety factor of two, d doubles to 2×10-5, so A = dC/ε = 2×10-5 × 10-8/(20 × 6.85×10-12) ≅ 1.5×103 [m2]. If the capacitor is a cube of side D, then the capacitor volume is D3 = Ad and D = (Ad)0.333 = (1.5×10-3 × 2×10-5)0.333 ≅ 3.1 mm. To simplify manufacture, such capacitors are usually wound in cylinders or cut from flat stacked sheets.


    This page titled 3.1: Resistors and Capacitors is shared under a CC BY-NC-SA 4.0 license and was authored, remixed, and/or curated by David H. Staelin (MIT OpenCourseWare) via source content that was edited to the style and standards of the LibreTexts platform; a detailed edit history is available upon request.